1. Field of the Invention
The present invention relates to a PLL circuit, and more particularly to a PLL circuit provided with an offset correcting circuit to correct a phase offset between a reference clock signal and a feedback clock signal.
2. Description of Related Art
In recent years, PLL (Phase Locked Loop) circuits have been used as an oscillation circuit incorporated into a semiconductor device in many cases. The PLL circuits control an oscillation frequency of an output signal to synchronize a phase of a reference signal with a phase of the output signal.
FIG. 13 is a block diagram of a general PLL circuit 100 as Related Art 1. As shown in FIG. 13, the PLL circuit 100 includes a phase comparator 111, a charge pump circuit 112, a loop filter 113, and a voltage-controlled oscillation circuit 114.
The phase comparator 111 compares a reference clock signal Fr with a feedback clock signal Fd obtained by feeding back an output clock signal Fo of the PLL circuit 100 and then outputs an up signal and a down signal for controlling the charge pump circuit 112. The charge pump circuit 112 outputs a current based on a pulse width difference between the up signal and the DN signal and outputs a charge pump output voltage in accordance with an amount of the output current. This current is supplied in an inflow direction or outflow direction based on the pulse width difference between the up signal and the down signal under control. The loop filter 113 accumulates charges in a capacitor in accordance with a current output from the charge pump circuit 112 and generates a voltage in accordance with the accumulated charges. The voltage is an output voltage of the charge pump circuit 112. Further, the loop filter 113 filters out RF noise and ripple noise superimposed on the charge pump output voltage. The voltage-controlled oscillation circuit 114 sends out an output clock signal Fo having a frequency corresponding to a voltage output through the loop filter 113. In addition, the output clock signal Fo is input to the phase comparator 111 as the feedback clock signal Fd.
In an ideal PLL circuit 100, if a phase of the reference clock signal Fr matches with a phase of the feedback clock signal Fd (or the output clock signal Fo), an amount of a sink current and a source current of the charge pump circuit 112 are the same. However, even if a phase of the reference clock signal Fr does not match with a phase of the feedback clock signal Fd, a sink current and a source current of the charge pump circuit 112 are not the same due to variations in circuit configuration of the charge pump circuit 112 or a transistor. In this case, the reference clock signal Fr and the feedback clock signal Fd are out of phase with each other in a stabilized state. The phase difference is called “phase offset”.
Japanese Unexamined Patent Application Publication No. 2005-123944 (Related Art 2) discloses a technique of correcting the phase offset. FIG. 14 is a block diagram of a PLL circuit 200 of the Related Art 2. As shown in FIG. 14, the PLL circuit 200 includes a delay circuit 211, a phase comparator 212, a charge pump circuit 213, a loop filter 214, a voltage-controlled oscillation circuit 215, a phase correction circuit 216, and an amplifier 220.
The delay circuit 211 receives a reference clock signal Fr and a feedback clock signal Fd, and gives a delay to each of the reference clock signal Fr and the feedback clock signal Fd to output a delay reference clock signal DLY1 and a delay feedback clock signal DLY2. Then, operations of the phase comparator 212, the charge pump circuit 213, the loop filter 214, and the voltage-controlled oscillation circuit 215 are stabilized on such conditions that a sink current and a source current of the charge pump circuit 213 are substantially the same on the basis of the delay reference clock signal DLY1 and the delay clock signal DLY2.
Further, the delay circuit 211 gives a delay that is determined by the phase correction circuit 216 and the amplifier 220. The phase correction circuit 216 includes a delay circuit 217, a phase comparator 218, and a charge pump circuit 219, the circuit configurations of which are substantially the same as those of the delay circuit 211, the phase comparator 212, and the charge pump circuit 213. In this case, the delay circuit 217 receives only the reference clock signal Fr. Then, a capacitor CDM for smoothing an output voltage of the charge pump circuit 219 is used to output a voltage corresponding to the output voltage of the charge pump circuit 219 (for example, dummy charge pump output voltage VCDM). That is, the dummy charge pump output voltage simulates a voltage output from the charge pump circuit 213 if a phase of the reference clock signal Fr matches with a phase of the feedback clock signal Fd.
The amplifier 220 outputs a control signal Vcont to the delay circuit 211 and the delay circuit 217 based on a differential voltage between the dummy charge pump output voltage VCDM and a monitor voltage VC of the charge pump circuit 213. The delay circuit 211 and the delay circuit 217 determine a delay corresponding to a voltage value of the control signal Vcont.
That is, the PLL circuit 200 determines a delay of the delay circuit 211 based on the monitor voltage VC of the charge pump circuit 213 and the dummy charge pump output voltage VCDM such that a phase of the reference clock signal Fr matches with a phase of the feedback clock signal Fd. Then, a phase offset between the reference clock signal Fr and the feedback clock signal Fd is corrected by the delay circuit 211 giving an appropriate delay to the reference clock signal Fr and the feedback clock signal Fd.
However, in the PLL circuit 200 of the Related Art 2, in addition to the phase comparator 212 connected to the PLL circuit, it is necessary to provide the phase comparator 212 to the phase correction circuit 216 to generate a dummy charge pump output voltage VCDM. Thus, the PLL circuit 200 involves a problem that a circuit is upsized. Further, power supply noise is caused by operations of the phase comparator. That is, there is a problem that the power supply noise increases as the number of phase comparators increases.